(Nonvolatile) Memory devices include output buffers of the type exemplified in FIG. 1a. They generate on a respective line of the bus DQ_PAD data read from the memory and made available on an internal bus DBUS. The internal signal OE (“Output Enable”) for enabling an output buffer, or its inverted replica OEN generated by the dedicated circuit of FIG. 1b, disables the memory buffer and sets in a high impedance state the respective line DQ_PAD when the external enabling command CEN_PAD (“Chip Enable”) is high, that is when the memory device is disabled.
When the memory is enabled, an output buffer transfers data from a line of the bus DBUS to the line of the bus DQ_PAD when a respective external enabling command OEN_PAD switches to the null logic value. Other circuits of the memory, not shown, send through the bus DBUS data read from the memory. This data is made available on the lines DQ_PAD after a time tELQV, for instance of 60 ns, from the instant in which the memory has been enabled.
An output buffer transfers on the line DQ_PAD a signal present on the internal bus DBUS after a time tELQX shorter than the time tELQV. In a buffer of FIG. 1a, the time tELQX is determined by the turn on/off delays of the MOS transistor and it is typically on the order of 15 ns.
It is evident that a line DQ_PAD is needlessly occupied for a relatively long time with data that does not correspond to the data read from the memory because this is not yet available on the internal bus DBUS. It would be desirable to increase the time tELQX to make it close to the time tELQV such that the line DQ_PAD is occupied only when a stable signal, corresponding to the read data, is present on the internal bus DBUS. This would reduce power consumption and noise on the line DQ_PAD and would free it for other uses.
For instance, a device for writing in the memory and a device for reading from the memory could use the same line DQ_PAD in a time-sharing mode. It would be possible to exploit the waiting time for a reading operation as a “hold-time” of a writing operation, with evident advantages in terms of reduced hardware complexity and optimization of the read/write phases.